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T6963CFG 2007-05-15 1 toshiba cmos digital integrat ed circuit silicon monolithic T6963CFG dot matrix lcd controller lsi the T6963CFG is an lcd controller designed to be used with lcd control driver lsis and data display memories. the device has an 8 ? bit parallel data bus and control lines for reading or writing through an mpu interface. it can be directly connected to a tmpz ? 80. it has a 128 ? word character generator rom which can control an external display ram of up to 64 kbytes. allocation of text, graphics and external character generator ram can be made easily and the display window can be moved freely within the allocated memory range. the device supports a very broad range of lcd formats by allowing selection of different combinations via a set of programmable inputs. it can be used in text, graphic and combination text ? and ? graphic modes, and includes various attribute functions. the T6963CFG is lead (pb)-free (sn-ag) product. features z display format (pin ? selectable) columns : 32, 40, 64, 80 lines : 2, 4, 6, 8, 10, 12, 14, 16, 20, 24, 28, 32 the combination of number of columns and number of li nes must not cause the freq uency to exceed 5.5 mhz. (see fig. 2) z character font (pin ? selectable) horizontal dots : 5, 6, 7, 8 vertical dots : 8 (fixed) it is necessary to set a character font in graphic mode just as in text mode. the os cillation frequency does not change with the font selection. z display duty : 1 / 16 to 1 / 128 z a 128 ? word character generator rom (code 0101) T6963CFG ? 0101 is built in as standard. z external display memory : 64 kb max the addresses in display memory of the text area, gr aphic area and external character generator area are determined by software. z read or write operations from th e cpu do not disturb the display. z a crystal oscillator circuit is built in . the oscillation frequency is adjusted according to the display size. if using an external clock, use the xi pi n as the clock input. (xo open.) external capacitors crystal oscillation : 20 to 30 pf ceramic oscillation : 30 to 100 pf built ? in feedback resistor : 900 k ? (typ.) z toshiba lcd driver lsis (oth er than these with a built ? in ram) can be connected to the device. z external display ram must be static ram. the T6963CFG cannot refresh d ? ram. z the attribute functions can only be used in text mo de. they cannot be used in graphic or combination character mode. weight: 1.2 g (typ.)
T6963CFG 2007-05-15 2 block diagram T6963CFG 2007-05-15 3 pin assignment pin functions pin name i / o functions pins for selection of lcd size mds md0 md1 input dual h h h h h h h h l l l l l l l l mds l l l l h h h h l l l l h h h h md1 h h l l h h l l h h l l h h l l md0 h l h l h l h l h l h l h l h l lines 2 4 6 8 10 12 14 16 4 8 12 16 20 24 28 32 v ? dots 16 32 48 64 80 96 112 128 32 64 96 128 160 192 224 256 1 screen 2 screens md2 md3 input pins for selection of number of columns md2 h l h l md3 h h l l columns 32 40 64 80 fs0 fs1 input pins for selection of font fs0 h l h l fs1 h h l l font 5 8 6 8 7 8 8 8 d0 to d7 i / o data i / o pins between cpu and T6963CFG (d7 is msb) wr input data write. write data into T6963CFG when wr = l. rd input data read. read data fromT6963CFG when rd = l. ce input chip enable for T6963CFG. ce must be l when cpu communicates with T6963CFG. T6963CFG 2007-05-15 4 pin name i / o functions c / d input wr = l c / d = h: command write c / d = l: data write rd = l c / d = h: status read c / d = l: data read halt input h normal, l stops the oscillation of the clock reset input h normal (T6963CFG has internal pull ? up resistor) l initialize T6963CFG. text and graphic have addresses and text and graphic area settings are retained. dspon output control pin for external dc / dc. dspon is l when halt is l or reset is l. (when dspon goes h, the column drivers are cleared.) dual input h single ? scan l dual ? scan dual h h l l sdsel h l h l h sending data by odd / even separation l sending data by simple serial method sdsel input upper screen hod, ed ed hod, ed ed lower screen D D lod, ed ed ce0 (lod) output ce0 at dual = h chip enable pin for display memory in the address range 0000h to 07ffh lod at dual = l serial data output for odd columns in lower area of lcd ce1 (lscp) output ce1 at dual = h chip enable pin for display memory in the address range 0800h to 0fffh lscp at dual = l shift clock pulse output for column drivers in lower area of lcd ce output chip enable pin for display memory of any address d0 to d7 i / o data i / o pins for display memory ad0 to ad15 output address outputs for display memory (ad15 = l: for upper area of lcd, ad15 = h: for lower area of lcd) r / w output read / write signal for display memory ed output sdsel = h: data output for even columns in both upper and lower areas of lcd sdsel = l: data output for columns in both upper and lower areas of lcd hod output data output for odd columns in upper area of lcd cdata output synchronous signal for row driver hscp output shift clock pulse for column driver of upper area of lcd lp output latch pulse for column driver. shift clock pulse for row driver fr output frame signal xi input crystal oscillator input xo output crystal oscillator output ch1, ch2 output check signal t1 , t2 input test input. usually open v dd D power supply (5.0 v) v ss D power supply (0 v) T6963CFG 2007-05-15 5 functional definition after power on, it is necessary to reset. reset is kept l between 5 clocks up (oscillation clock). when halt = l, the oscillation stops. the power supply for the lcd must now be turned off, to protect the lcd from dc bias. the halt function includes the reset function. the column / line counter and display register are cleared by reset. (other registers are not cleared.) disable the display using the clear ? display register. the status must be checked before data or commands are sent. the msb = 0 status check must be done in particular. there is a possibility of erro neous operation due to a hard interrupt. sta0 and sta1 must be checked at the same time. when a command is executed, data transmission errors may occur. the T6963CFG can only handle one byte per machine cycle (16 clocks). it is impossible to send more than two data in a machine cycle. when using a command with operand data, it importan t to send the data firs t, and then execute the command. the character codes used by the T6963CFG are different from ascii codes. T6963CFG 2007-05-15 6 state after reset / halt (fig. 1) terminal halt reset d0 to d7 f f d0 to d7 f f r / w h h ce h (note 1) h (note 1) ad0 to ad15 h (note 2) h (note 2) ce0 , ce1 h (note 1) h (note 1) ed, hod final data final data hscp l l lp l l cdata h h fr h h ch1 l k0 ch2 l vend dspon l l xo h osc clock h : level h l : level l f : floating (high impedance) k0 : test signal vend : test signal note 1: in attribute mode, h or l according to state of graphic pointer note 2: in attribute mode, data of graphic pointer T6963CFG 2007-05-15 7 the relationship between number of row / column and oscillation clock (fig. 2) the frequency of the crysta l oscillator is adjusted by the following formula. f osc : frequency of oscillation f scp : frequency of shift clock (f scp = f osc / 2) f r : frequency of frame m : number of characters on one line (number of dots on one line 8 m) for all font sizes (e.g. 7 8, 6 8, 5 8) the oscillation freque ncy remains constant. n : number of rows (duty = 1 / 8n) r f scp f 1 n 8 m 8 = f osc = f r 64 2 m n (f r = 60 hz) unit: [mhz] m n 32 40 64 80 duty 0.492 0.614 0.983 1.229 2 0.983 1.229 1.966 2.458 1 / 16 0.983 1.229 1.966 2.458 4 1.966 2.458 3.932 4.915 1 / 32 1.475 1.843 2.949 3.686 6 2.949 3.686 5.898 7.372 1 / 48 1.966 2.458 3.932 4.915 8 3.932 4.915 7.864 9.830 1 / 64 2.458 3.072 4.915 6.144 10 4.915 6.144 9.830 12.288 1 / 80 2.949 3.686 5.898 7.373 12 5.898 7.373 11.776 14.746 1 / 96 3.440 4.300 6.881 8.602 14 6.881 8.601 13.763 17.203 1 / 112 3.932 4.915 7.864 9.830 16 7.864 9.830 15.729 19.660 1 / 128 note 1: upper single ? scan, lower dual ? scan at f r = 60 hz note 2: m and n to mach 5.5 mhz or less indicate the conditions to apply T6963CFG. upper lower T6963CFG 2007-05-15 8 ram interface the external ram is used to store display da ta (text, graphic and external cg data). with single ? scan, text data, graphic data and external cg da ta can be freely allocated to the memory area (64 kb max). with dual ? scan, lcd i is allocated to 0000h to 7fffh (32 kb max), lcd ii is allocated to 8000h to ffffh (32 kb max). text data, graphic data and external cg data can be freely allocated in lcd i. in lcdii, the same addresses must be allocated as in lcd i, except ad15. ad15 determines selection of lcd i or lcd ii. it can be use the address decoded signals ce0 (0000 to 07ffh), ce1 (0800 to 0fffh) within 4 kb. ce0 and ce1 allow decoding of addresses in the ranges ( 0000 to 07ffh) and (0800 to 0fffh) respectively within a 4 ? kb memory space. (example) (1) single ? scan (2) dual ? scan T6963CFG 2007-05-15 9 flowchart of communications with mpu (1) status read a status check must be performed before data is read or written. 4 u b u v t d i f d l the status of T6963CFG can be read from the data lines. rd l wr h ce l c / d h d0 to d7 status word the T6963CFG status word format is as follows: msb lsb sta7 d7 sta6 d6 sta5 d5 sta4 d4 sta3 d3 sta2 d2 sta1 d1 sta0 d0 sta0 check command execution capability 0: disable 1: enable sta1 check data read / write capability 0: disable 1: enable sta2 check auto mode data read capability 0: disable 1: enable sta3 check auto mode data write capability 0: disable 1: enable sta4 not used sta5 check controller operation capability 0: disable 1: enable sta6 error flag. used for screen peek and screen copy commands. 0: no error 1: error sta7 check the blink condition 0: display off 1: normal display note 1: it is necessary to check sta0 and sta1 at the same time. there is a possibility of erroneous operation due to a hardware interrupt. note 2: for most modes sta0 / st a1 are used as a status check. note 3: sta2 and sta3 are valid in auto mode; sta0 and sta1 are invalid. T6963CFG 2007-05-15 10 4 u b u v t d i f d l j o h g m p x b c note 4: when using the msb = 0 command, a status read must be performed. if a status check is not carried out, the T6963CFG cannot operate normally, even after a delay time. the hardware interrupt occurs during the addre ss calculation period (at the end of each line). if a msb = 0 command is sent to the T6963CFG dur ing this period, the T6963CFG enters wait status. if a status check is not carried out in this st ate before the next command is sent, there is the possibility that the command or data will not be received. (2) setting data when using the T6963CFG, first se t the data, then set the command. 1 s p d f e v s f g p s t f o e j o h b d p n n b o e b |